levelsensitive

Level-sensitive describes a property of certain digital circuits in which the output responds to the input as long as a control signal remains at a given logic level, rather than only at a clock edge. In sequential logic, level-sensitive devices sample and potentially propagate input signals when an enable or clock input is at its active level, and they hold a value when the enable level is inactive. This is in contrast to edge-triggered devices, which change state only on the transition of a clock signal.

The classic example is the level-sensitive latch, such as the D latch. A D latch becomes transparent when the enable input is at its active level, meaning the output tracks the input. When the enable returns to its inactive level, the last captured value is held. Other level-sensitive elements include various gated latches and clocked storage cells that rely on a level to gate data flow. Level-sensitive devices are fundamental building blocks in many register files and simple memory structures.

In practice, level-sensitive designs are often used to implement more complex timing architectures, such as master-slave configurations that create edge-triggered behavior from two level-sensitive latches. They require careful attention to timing parameters, including propagation delays and setup and hold times relative to the enable level, to avoid glitches and unintended data changes. Their simplicity and transparency during the active level make them versatile, but they can be more susceptible to hazards if clock or enable signals are not carefully managed.