speichercontroller

SpeicerController, commonly called the memory controller, is a hardware component that manages the transfer of data between a processor and the system's memory, typically volatile DRAM. It coordinates the timing, sequencing, and control signals required to read from and write to memory, issues commands, handles address translation, and ensures data integrity through features such as ECC where available. It also orchestrates refresh cycles for DRAM and manages voltage and timing parameters within supported ranges.

Most modern systems place the memory controller inside the CPU die (an integrated memory controller, IMC), reducing latency and increasing bandwidth. In other architectures, the controller resides in the motherboard chipset or memory controller hub. The device exposes memory channels and ranks, and supports different DDR generations (e.g., DDR4, DDR5) with appropriate data rates and timings. The controller may implement interleaving, addressing schemes, and NUMA awareness to optimize multi-socket or asymmetrical memory layouts.

Operational duties include command scheduling, precharge, activation, refreshing, and data buffering. It negotiates timing and frequency with the memory modules and ensures compatibility with the CPU memory controller's policies. It may provide ECC to detect and correct errors, error reporting, and memory protection features, and can support registered or unbuffered modules in server-class systems.

Variants and scope: In GPUs, system-on-chip designs, and enterprise servers, specialized memory controllers manage large-scale memory subsystems and often include advanced features such as partial writes, refresh algorithms, and memory pooling for virtualization or NUMA workloads.