pBIST

pBIST, or pseudo Built-In Self-Test, is a fault-detection technique used in digital integrated circuits to enable on-chip testing with minimal external test equipment. It relies on embedded test infrastructure that generates test patterns on chip and analyzes responses locally, often allowing production testing and occasional in-field diagnostics without external testers. The “pseudo” aspect typically denotes the use of on-chip, pseudo-random-pattern generation rather than fully deterministic external test vectors.

A typical pBIST architecture includes a test pattern generator, commonly based on a linear feedback shift register (LFSR), and a response analysis block such as a multiple-input signature register (MISR) that compresses the circuit’s outputs into a compact signature. A control unit sequences test rounds, manages wrap-around, and coordinates comparison of the final signature against a pre-stored golden signature. This framework supports both logic-based BIST (LBIST) and, for memory blocks, MBIST variants. Some implementations also incorporate a small repository of deterministic patterns to boost fault coverage beyond pseudo-random testing.

Applications of pBIST include cores and IP blocks within system-on-chip designs, as well as memory arrays and configurable logic in FPGAs. It is used for manufacturing test, post-silicon validation, and occasional on-line health monitoring.

Advantages of pBIST include reduced reliance on external testers, shorter test times, and the ability to perform tests at various stages of the lifecycle. Limitations involve incomplete fault coverage if the pattern set is limited, potential area and power overhead, and the need for careful integration to avoid interference with normal operation.