irq

An interrupt request (IRQ) is a hardware or software signal to the processor indicating that immediate attention is needed. In most architectures, devices use IRQ lines to request service for events such as keystrokes, I/O completion, or timer ticks. An interrupt controller collects these signals, arbitrates among multiple requests, and delivers them to the CPU as interrupts. In x86 systems, legacy IRQs are managed by PICs (programmable interrupt controllers) and, in modern platforms, by I/O APICs and Local APICs that support many more lines, routing, and both edge-triggered and level-triggered signaling.

The typical flow is: a device asserts an IRQ; the interrupt controller acknowledges and forwards the interrupt to the CPU; the processor interrupts current work, saves state, and uses an interrupt vector to dispatch an interrupt service routine (ISR). When the ISR finishes, software or the controller issues an End Of Interrupt (EOI) to allow further interrupts. IRQ numbers are platform-specific; common PC mappings allocate IRQ 0 to the system timer, IRQ 1 to the keyboard, IRQ 2 as a cascade to a second PIC, and higher numbers to other devices. Modern systems may use Message Signaled Interrupts (MSI), which encode interrupts as in-band messages rather than dedicated lines, increasing flexibility and scalability.

Shared interrupts occur when multiple devices share a single IRQ, requiring the ISR to identify the source. Masking can temporarily block IRQs, and interrupt priority or nesting controls limit preemption. In ARM architectures, the Generic Interrupt Controller (GIC) distributes and prioritizes interrupts across cores and supports software-generated interrupts and virtualization. Software interrupts and traps are conceptually distinct from hardware IRQs but interact with the same handling framework.