Yosys
Yosys is an open-source framework for Verilog synthesis. It provides a set of command-line tools for processing and optimizing Verilog hardware description language designs. Yosys can read various Verilog formats, including SystemVerilog, and translate them into a gate-level netlist. It is designed to be extensible, allowing users to add new synthesis algorithms and optimizations.
The primary function of Yosys is to convert a high-level description of digital hardware into a low-level
Yosys is often used as part of a larger open-source electronic design automation (EDA) flow. It can