Xcelium

Xcelium is a high-performance digital circuit simulator developed by Cadence Design Systems for validating RTL and mixed-language designs. It is designed to deliver fast, scalable verification for complex ASIC and FPGA projects and is widely used in the semiconductor industry. Xcelium traces its lineage to the Incisive family and represents Cadence’s modern HDL simulation platform.

It supports SystemVerilog, Verilog, VHDL, and mixed-language designs, providing cycle-accurate timing and robust debugging. It includes native support for SystemVerilog Assertions, SystemVerilog DPI, and common verification methodologies such as UVM-based testbenches, coverage collection, and functional coverage reporting.

Xcelium employs a multi-core, multi-threaded simulation engine to improve throughput for large designs and regression suites. It offers fast startup and efficient use of memory, along with advanced debugging capabilities. It integrates with Cadence's SimVision waveform viewer for analysis and with the broader Cadence verification flow, enabling coordinated test execution, result reporting, and regression management.

As part of Cadence's Verification Suite, Xcelium is used by semiconductor companies for design verification, digital IP validation, and pre-silicon verification in mixed-language environments. It is designed to fit into established verification methodologies and to work alongside other Cadence tools and third-party flows.