X2APIC

X2APIC is a scalable extension of the Advanced Programmable Interrupt Controller (APIC) used in modern Intel multi-core and multi-socket systems. It builds on the traditional APIC architecture to improve the delivery and management of interrupts across large, complex processors.

Compared with legacy APIC modes, x2APIC shifts most registers to a Model-Specific Register (MSR) interface and reduces reliance on legacy I/O and memory-mapped I/O registers. This MSR-based interface expands the destination addressing space, enabling up to 2^32 possible interrupt destinations, which supports large-scale multiprocessing and NUMA configurations. The mode can improve interrupt latency and reduce bus traffic by enabling more direct routing of interrupts to the appropriate local APIC.

Activation of x2APIC depends on processor support and firmware/operating system configuration. CPUID indicates x2APIC capability, and the IA32_APIC_BASE MSR can be configured to enable x2APIC mode on supported hardware. Modern operating systems, including Linux and Windows, typically enable x2APIC automatically when the hardware supports it; older environments may require kernel parameters, firmware updates, or manual configuration.

Operational considerations include compatibility with traditional APIC concepts. The local APIC remains the mechanism at each core, while interrupts can be delivered via MSI or other supported pathways as appropriate. In virtualized environments, hypervisors may expose x2APIC to guests or emulate it, which can influence interrupt performance and scheduling behavior.

X2APIC is one component of the broader interrupt architecture landscape, alongside the local APIC, I/O APIC, and message-signaled interrupt (MSI) mechanisms, and it plays a key role in enabling scalable interrupt handling in modern CPUs.