RRAM

Resistive random-access memory (RRAM) is a non-volatile memory that stores data by changing the resistance of a dielectric switching layer within a metal–insulator–metal stack. Data are encoded in two resistance states: high (HRS) and low (LRS). The state is switched by applying voltage or current, typically in a bipolar fashion (set to LRS, reset to HRS) or, in some devices, unipolar. The switching is commonly attributed to formation and rupture of conductive filaments (such as oxygen vacancies or metal ions) or to interface-type changes that alter barrier height at the metal–insulator interface.

Device architectures commonly use crossbar arrays; to avoid current sneak paths, selector devices (diodes or transistors) are integrated, resulting in 1T1R or 1D1R configurations. The basic structure is a simple metal–insulator–metal sandwich, but practical implementations use oxide or nitride layers (e.g., HfO2, TiO2, Ta2O5) and sometimes porous or doped materials. A forming step is often required to initialize the device.

Materials: oxide-based switching materials including hafnium oxide, tantalum oxide, titanium oxide, as well as other systems like perovskites or chalcogenides. The switching mechanism, device-to-device variability, endurance and retention depend on material and structure. Manufacturing is pursued for CMOS compatibility.

Performance and applications: RRAM promises fast programming and reading speeds, low operating voltages, excellent scalability to nanoscale features, and non-volatility, making it candidates for storage-class memory and embedded memory, as well as neuromorphic computing for synaptic weight storage. Challenges include controlling variability, improving retention and endurance, and developing reliable selectors to enable dense arrays.

Status: RRAM is under active research and development with several commercial demonstrations and ongoing efforts by companies and research institutes. While not yet universally adopted as a mainstream memory technology, it is considered a leading candidate for future non-volatile memory architectures.