Placeandroute

Place-and-route, often abbreviated P&R, is a stage in the physical design phase of semiconductor design. It converts a technology-mapped netlist into a physical layout by determining where to place standard cells and macros and how to route their interconnections. The goal is to meet timing, area, and power constraints while ensuring manufacturability and routability.

In ASIC flows, P&R follows floorplanning and placement and precedes routing and timing verification. Placement assigns each cell to a specific location on the chip, aiming to minimize wire length, balance utilization, and reduce congestion. Legalization may adjust placements to align with the manufacturing grid. Routing then connects the placed cells through the available metal layers, typically in two stages: global routing to plan high-level paths and detailed routing to resolve exact wire geometries and vias while respecting design rules and timing constraints.

Outputs of the P&R process include a physical design database and standard interface files such as DEF (design exchange format), GDSII (layout data), and LEF (library exchange). The results are used for timing analysis, power integrity, signal integrity checks, and subsequent steps like clock tree synthesis, extraction, and tape-out. Verification tasks such as DRC (design rule checking) and LVS (layout vs. schematic) are run to ensure correctness before fabrication.

In FPGA flows, place-and-route refers to mapping the logical design to the programmable fabric, assigning logic blocks and registers to physical resources and configuring interconnect routes. P&R tools in both ASIC and FPGA contexts strive for a balance between speed, area, and power while accommodating timing budgets and routing constraints. Open-source efforts, such as the OpenROAD project, seek to provide end-to-end P&R capabilities.