tapeout

Tapeout is the point at which the physical layout data for an integrated circuit is released to a semiconductor fabrication facility to begin manufacturing. Historically, the term referred to recording the design onto magnetic tape; in modern practice it denotes the transfer of final layout data to the foundry, typically in standardized formats such as GDSII or OASIS.

Before tapeout, the design undergoes extensive verification and optimization. This includes logic synthesis, place and route, timing analysis, power integrity checks, and design-for-manufacturability evaluations. Physical verification steps, such as design rule checks (DRC) and layout versus schematic checks (LVS), are performed, and a design sign-off is achieved by both the design team and the foundry. The objective is to ensure the layout meets electrical and manufacturing requirements across process corners and variations.

The tapeout package comprises the complete physical layout data, usually in GDSII or OASIS format, along with mask set descriptions, test structures, and fabrication notes. The data are used to produce photomasks for each lithography layer. Depending on the process node and technology, multiple masks and specialized steps may be required. Data integrity and security are critical, as errors can lead to costly re-spins or yield losses.

After tapeout, photomasks are manufactured and used to fabricate wafers. If errors are found later, a re-tapeout and re-fabrication may be necessary, causing delays and additional costs. Tapeout thus marks the transition from chip design to manufacturing and represents a major project milestone.