PDPT

PDPT commonly refers to the Page Directory Pointer Table, a component of the x86-64 memory management unit used in virtual memory address translation. It is part of the hierarchical page table structure employed by modern operating systems to map a process’s virtual addresses to physical memory. The term is most often encountered in discussions of IA-32e paging, though it can appear in related documentation about paging modes and processor architectures.

In 64-bit mode, address translation uses a four-level page table: PML4, PDPT, PD, and PT. The PDPT contains 512 entries; each entry points to a Page Directory (PD). Each PDPT entry is 64 bits wide and stores flags such as present, read/write, user/supervisor, and the physical address of the next-level page table. A PDPT is typically 4 KB in size because 512 entries × 8 bytes equals 4096 bytes. The PDPT is referenced indirectly via the PML4 entry in the control register that holds the base address of the top-level table.

The PDPT plays a role in translating virtual addresses to physical ones by linking to lower-level structures that finally map to page frames. In modern CPUs, the introduction of 5-level paging adds a top-level PML5, but the PDPT remains part of the hierarchical scheme. The structures involved are cached in the translation lookaside buffer (TLB) to speed up repeated address translations.

Other uses: PDPT is an acronym used in other domains as well, but in common computing literature it most often denotes the Page Directory Pointer Table.