PML4

PML4, short for Page Map Level 4, is the top-level page table in the 4-level paging scheme used by x86-64 processors in long mode. It is a key component of virtual-to-physical address translation in modern 64-bit operating systems.

Structure and role. A PML4 table is 4 KiB in size and contains 512 entries, known as PML4E. Each entry holds the physical address of a corresponding page-directory-pointer table (PDPT) along with a set of control bits that indicate properties such as presence, read/write permissions, user/supervisor mode, and cache and execution attributes. The PDPT, in turn, leads to the next levels of the hierarchy (PD and PT) that ultimately map to physical pages.

Address translation flow. In 4-level paging, a virtual address is split into five fields: a 9-bit PML4 index (bits 39–47), a 9-bit PDPT index (bits 30–38), a 9-bit PD index (bits 21–29), a 9-bit PT index (bits 12–20), and a 12-bit page offset (bits 0–11). The processor uses the PML4 index to select a PML4E, checks the present bit, and, if present, uses the PDPT pointed to by that entry. The next levels are consulted in order until a valid 4 KiB page, or a larger page if permitted, is found.

Large-page support. Large pages are implemented through flags in PDEs and PDPTEs. A PDPT entry with the large-page flag can map a 1 GiB region, while a PDE with the large-page flag can map a 2 MiB region, bypassing lower levels.

Usage. PML4 is used by the CPU memory management unit as part of the canonical 4-level page table structure in 64-bit operating systems, enabling efficient and flexible virtual memory management.

Notes. Each PML4 table is itself a 4 KiB page, containing 512 entries, and the addressing scheme is 64-bit, with canonical addresses and extended physical addressing depending on hardware support.