NetworkonChip

Network-on-Chip (NoC) is a scalable communications subsystem on a single chip that interconnects intellectual property cores, memories, and peripherals through a network-like fabric. NoCs replace traditional shared buses or point-to-point links to improve bandwidth, reduce latency, and support growing core counts while managing power and area.

A NoC typically comprises routers located at core boundaries, network interfaces attached to cores, and a network of links forming a topology such as mesh, torus, ring, or fat-tree. Routers perform packet switching, arbitration, and routing computation; network interfaces convert core transactions into flits or packets and back.

Routing and flow control: NoCs support static or adaptive routing. Common schemes include XY routing for grids and adaptive wormhole routing with virtual channels to prevent deadlock. Flow control is often credit-based or uses lightweight handshaking; virtual channels separate traffic classes to provide quality of service.

Design considerations and trade-offs: topology influences latency, bandwidth, and routability; mapping and partitioning affect performance; router microarchitecture, buffer sizes, and link granularity determine area and power; thermal and power constraints are important in embedded systems.

Applications and outlook: NoCs are used in many-core processors, multiprocessor systems-on-chip, and heterogeneous MPSoCs, enabling modular design and IP reuse. Ongoing research focuses on energy efficiency, QoS, security, and integration with on-chip wireless or optical links, as well as tools for design, simulation, and mapping.