NVIC

The Nested Vectored Interrupt Controller (NVIC) is a component of ARM Cortex-M microcontrollers that manages interrupt handling for both core exceptions and external interrupt requests. It enables preemption and nesting of interrupts, providing low-latency response to asynchronous events from peripherals and the system.

Key features of the NVIC include programmable interrupt enabling and disabling, pending and active state tracking, and a priority scheme that allows interrupts to preempt one another. Software can set priorities and enable or disable specific interrupts, which the NVIC uses to determine service order. The priority mechanism often supports a grouping scheme that splits a priority field into preemption priority and subpriority, enabling complex nesting behavior. The exact behavior depends on the device and core generation.

The NVIC interfaces with the system control block and vector table. When an interrupt occurs, the NVIC uses the interrupt number to fetch the corresponding handler address from the vector table and to apply the configured priority logic. The vector table base address is configurable through the vector table offset register. Priority grouping is configured via special registers in the system control block, which define how many bits implement preemption versus subpriority. The NVIC provides a set of registers for each interrupt, including enable, disable, set-pending, clear-pending, and read-active status.

Implementation details vary by device, but in typical Cortex-M microcontrollers the NVIC supports a scalable number of external interrupt lines and integrates closely with the core to support tail-chaining and efficient, nested interrupt handling. NVIC-based interrupt control is central to real-time and embedded systems requiring responsive and deterministic interrupt processing.