MEMSIMUt

MEMSIMUt is a software framework for simulating memory systems in computer architecture research and education. It models components of modern memory hierarchies, including caches, main memory, and virtual memory management, to help users evaluate performance implications of design choices.

The architecture is modular. A memory model defines hierarchical levels and latencies; a cache and TLB simulator handles cache coherence, miss penalties, and translation lookaside buffer behavior; a memory-management unit component models page tables, TLB misses, page faults, and paging policies; a disk/I/O model represents secondary storage latency; a workload generator provides synthetic or trace-based workloads; and an analysis module collects statistics and supports visualization.

Key features include configurable cache parameters (size, associativity, write strategy), virtual memory configurations (single-level or multi-level page tables, page sizes), and page replacement algorithms (LRU, FIFO, CLOCK, OPT when traces available). It can import memory traces, simulate parallel workloads, and output metrics such as hit/miss rates, stall cycles, and bandwidth.

Applications: MEMSIMUt is used in university courses and research to illustrate memory hierarchy effects, compare architectures, and teach page replacement and TLB behavior.

Development and availability: MEMSIMUt is distributed as open-source software through public repositories. It has seen community contributions and is cross-platform, running on major operating systems with standard dependencies.

See also: memory hierarchy, virtual memory, cache, TLB, page replacement algorithm.