8259style

8259style refers to the interrupt controller interface modeled after the Intel 8259 Programmable Interrupt Controller. This term is used to describe the legacy, PIC-compatible approach to handling hardware interrupts in systems that either use real 8259A chips or emulate their behavior. The canonical arrangement uses two 8259 devices, a master and a slave, to provide up to 15 external interrupt lines: eight on the master and seven on the slave cascaded through the master’s IRQ2 line. The master and slave are programmed and managed through a pair of I/O ports per chip, with initialization words (ICW1–ICW4) to set basic operation and a set of operation command words (OCWs) to control masking, priority, and mode.

Key features of the 8259style interface include the Interrupt Mask Register (IMR) to enable or disable individual IRQs, the In-Service Register (ISR) and Interrupt Request Register (IRR) to track active and pending interrupts, and the End of Interrupt (EOI) mechanism used to acknowledge completion and allow subsequent interrupts. Each interrupt is associated with a vector number derived from a base offset configured during initialization; by convention, IRQs are divided between the master and slave, with the slave’s interrupts presented to the CPU as a contiguous range after the master’s.

In practice, 8259style remains a reference point for legacy interrupt handling in operating systems, embedded systems, and certain emulation or virtualization environments. Modern x86 systems typically replace or supplement it with the Advanced Programmable Interrupt Controller (APIC) to support more scalable interrupt distribution, but 8259style behavior is still encountered in bootstrapping paths and compatibility layers.