16550compatible

16550-compatible refers to UART devices that implement the same register map, interrupt behavior, and FIFO characteristics as the Intel 16550/16550A UART. This compatibility allows software, including operating system drivers and serial stacks, to treat the device as a standard 16550 without device-specific changes.

Background and scope

The 16550 family introduced a small receive and transmit FIFO to reduce CPU overhead from serial I/O. The 16550A refined the design for improved reliability and timing. A device labeled 16550-compatible typically adheres to the common 8-bit/1-stop bit, no-parity default data format and provides a baud rate divisor that can be set via a latch mechanism. The goal is portable software that can rely on a stable, well-documented interface across different hardware implementations.

Register map and operation

Most 16550-compatible UARTs expose a predictable set of registers. Offsets commonly include: 0 for RBR/THR, 1 for IER, 2 for IIR/FCR, 3 for LCR, 4 for MCR, 5 for LSR, 6 for MSR, and 7 for SCR. When the divisor latch enable (DLAB) bit in the line control register is set, offsets 0 and 1 access the Divisor Latch Low and High for configuring baud rate, otherwise they access the RBR/THR and IER. The FIFO control register (FCR) enables and configures the FIFO if available, and the IIR indicates interrupt reasons. A typical device may implement a 16-byte FIFO for both RX and TX.

Compatibility notes

While many devices advertise 16550-compatibility, there can be vendor-specific quirks in timing, FIFO depth, or register quirks. Some vendors offer partial implementations or require specific initialization sequences. Software should rely on standard 16550 behavior when possible, but consult manufacturer documentation for any deviations. In practice, 16550-compatible UARTs are widely supported by common serial drivers across operating systems.