tamperresistance

Tamper resistance refers to design features and processes intended to deter, detect, or delay unauthorized modification of a device, system, or product after it has been manufactured. It encompasses physical barriers, cryptographic protections, and procedural controls that raise the effort, cost, or risk of tampering. It is distinct from tamper-evident, which only provides visible signs that tampering has occurred, whereas tamper resistance means that tampering is technically difficult to carry out or detect.

Applications include packaging for pharmaceuticals and electronics; security-sensitive hardware such as smart cards, hardware security modules, secure enclaves, and payment terminals; software protections like code signing, secure boot, code integrity checks, and attestation; and supply chain controls such as serialization and tamper-evident seals.

Mechanisms fall into physical, procedural, and cryptographic categories. Physical measures include tamper-evident seals, tamper switches, intrusion-detecting enclosures, and secure enclosures. Procedural controls include restricted access during manufacturing and routine inspections. Cryptographic protections rely on secure elements, encryption keys inside protected hardware, digital signatures, and attestation to prove integrity.

Design considerations include threat modelling, cost-benefit analysis, maintenance, and user experience. Tamper resistance is not foolproof; determined adversaries can defeat it given sufficient resources, so layered security and regular audits are recommended.

Standards and certifications exist to evaluate and compare tamper resistance, including seals, crypto modules, and device packaging. Ongoing research focuses on stronger, verifiable protections that balance security with usability and supply-chain practicality.