TLBHits

TLBHits is a metric used in computer architecture and performance profiling that refers to the number or rate of translations found in a translation lookaside buffer (TLB) during address translation. A TLB is a small, fast cache that stores recent virtual-to-physical address translations to speed up memory access in systems using virtual memory.

A TLB hit occurs when the memory reference’s translation is already present in the TLB, allowing the processor to bypass a longer page table walk and deliver the corresponding physical address quickly. Conversely, a TLB miss happens when the translation is not in the TLB, requiring a page table walk or, in some cases, a more involved OS-soft or hardware-assisted translation process, which introduces additional latency.

TLBHits can be reported as a raw count or as a rate, such as a TLB hit rate equal to the number of hits divided by the total number of address translations. Modern CPUs typically maintain separate instruction TLBs (I-TLB) and data TLBs (D-TLB), and performance counters may expose hits for each domain. The interpretation of TLBHits depends on the counter’s scope and the workload being measured.

Factors that influence TLBHits include the size and associativity of the TLB, the working set of the application relative to the TLB capacity, page size (including large pages), and temporal locality of memory accesses. High TLBHit rates generally improve memory latency and overall performance, while TLB thrashing or frequent misses can become a bottleneck.

In practice, TLBHits are used in performance analysis to diagnose memory subsystem efficiency, compare architectures or compiler strategies, and guide optimizations aimed at improving locality, page size choices, or working set behavior.