Sub5nm

Sub5nm refers to semiconductor manufacturing process nodes with feature sizes below five nanometers. It is a colloquial term used to describe leading-edge fabrication technologies, rather than a formal industry standard. In practice, sub5nm generations cover multiple future and near-term nodes, commonly including 3nm and 2nm processes, with 1nm often described as being in research or pilot production. The term emphasizes the continued pursuit of higher transistor density and performance within the sub-5-nanometer regime.

Technologies associated with sub5nm nodes include advances in transistor architecture and lithography. Gate-all-around transistors based on nanosheet or nanowire structures increasingly replace traditional FinFETs to improve drive current and reduce leakage. Extreme ultraviolet (EUV) lithography has become central for printing ever-smaller features, supported by sophisticated patterning techniques and multi-patterning where needed. Device engineers also rely on materials and process innovations, such as high-k dielectrics, metal gates, strain engineering, and advanced interconnects, to sustain performance gains and energy efficiency.

Manufacturability at sub5nm scales faces significant challenges. Variability in transistor performance, leakage power, heat dissipation, and defect control can impact yield and reliability. The watermarked complexity of masks, tooling, metrology, and supply chains increases capital costs. As a result, sub5nm programs require close integration across design, manufacturing, and packaging, along with new approaches to verification and testing.

Industry status and outlook: leading semiconductor companies have announced sub5nm programs, including 3nm and 2nm nodes, with early products and pilot lines progressing in the 2020s. While sub5nm technologies promise substantial gains in density and efficiency, continued scaling will increasingly rely on architectural innovation, advanced materials, and three-dimensional integration to address physical limits.