SetReset

Setreset, often abbreviated as S/R or SR, refers to a control scheme used to store a binary state in sequential logic. It is implemented with a latch or flip-flop that has distinct set and reset inputs. The set input forces the stored value to 1, while the reset input forces it to 0. In a basic SR latch built from cross-coupled NOR gates, applying a high signal to S sets the output Q to 1; applying a high signal to R resets Q to 0. When both inputs are low, the latch preserves its previous state; when both inputs are high, the condition is invalid for NOR-based designs and can produce an indeterminate state.

A latch built from cross-coupled NAND gates uses active-low S and R inputs, where S=0 sets Q to 1 and R=0 resets Q to 0; both inputs 0 is also considered invalid for such configurations. These two implementations illustrate how the same set/reset concept can be realized with different input polarities.

Asynchronous versus synchronous operation is a key consideration. Many devices provide asynchronous set or reset lines, meaning they can force the output regardless of the clock, which is useful for initialization or recovery from errors. However, asynchronous control must be managed carefully to avoid glitches or metastability during normal operation. Some families label these controls as PRE/CLR, SET/RESET, or S/R, reflecting variations in timing and active polarity.

Set/reset functionality is foundational in SR latches, SR and D flip-flops, registers, and memory elements. It supports initialization, state control, and reliable startup of sequential circuits, and is a common tool in designing reset strategies for digital systems.