Selfrefresh

Self-refresh is a DRAM power-management feature in which the memory array refreshes itself using on-chip circuitry, rather than relying on the memory controller to issue external refresh commands. In normal DRAM operation, the memory controller periodically drives refresh commands to ensure data retention. In self-refresh, the DRAM internally handles refresh cycles, allowing the external address, data, and control lines to be idle or held in a defined state.

This mode is typically used to reduce power consumption during low-activity or low-power states, such as suspend-to-RAM or other sleep modes. While in self-refresh, the memory must maintain data integrity across a range of temperatures and supply voltages, with the internal refresh rate designed to meet retention requirements without external intervention. Exiting self-refresh usually requires a wake-up sequence by the memory controller, after which normal memory operation resumes; wake-up can involve a brief latency to reestablish timing and bank state.

Self-refresh is defined in JEDEC standards for SDRAM and its derivatives (including DDR generations) and is supported by many modern memory devices as part of broader low-power state management. Not all DRAM devices or system configurations enable true self-refresh, since some architectures rely exclusively on controller-driven refresh. When available, self-refresh can offer tangible power savings in idle periods, at the cost of wake latency and system complexity.