SDRAM

SDRAM, or synchronous dynamic random-access memory, is a type of DRAM whose operations are coordinated with an external system clock. By aligning command and data timing to clock edges, SDRAM can sustain higher and more predictable data rates than earlier asynchronous DRAM.

Internally, SDRAM is organized into memory banks and uses a multiplexed address bus to supply row and column addresses. A set of control signals, typically including chip select, clock enable, and the standard memory commands RAS, CAS, and WE, orchestrates row activation, data access, and precharge. The memory's sense amplifiers and precharge circuitry hold and restore data as it is read or written.

Data are accessed in bursts: after a row is activated, a sequence of data words can be delivered or accepted at consecutive addresses, governed by a fixed burst length and the clock rate.

Performance timing is specified by the clock and by CAS latency, which defines the number of clock cycles between a read command and data availability. The memory controller issues a sequence of timed commands for regular operation.

SDRAM was introduced in the 1990s and became standard in personal computers and other devices, eventually giving way to higher-performance generations such as DDR, DDR2, DDR3, and DDR4 SDRAM. The term SDRAM now generally refers to the original synchronous DRAM family from which these successors evolved.

Form factors include DIMMs for desktops and SO-DIMMs for laptops, with capacities ranging from a few megabytes in early devices to several gigabytes in modern systems. SDRAM remains a foundational technology in embedded and legacy systems.