R4300i

The R4300i is a 32-bit microprocessor designed by NEC Corporation that implements the MIPS III instruction set. It is the improved revision of the R4300 core, with the “i” suffix indicating an enhanced version compatible with MIPS III software. The R4300i was used in several NEC-based products in the 1990s, most notably as the central processing unit in the Nintendo 64 game console.

In terms of architecture, the R4300i is a MIPS III–based 32-bit RISC core. It features a conventional 32 general-purpose registers, a pipelined execution path, and, in configurations that include it, an integrated floating-point unit (Coprocessor 1). The processor was designed to balance performance with the cost and power constraints of consumer electronics and embedded systems. A common characterization of the core is a multi-stage pipeline (often described as five stages) to improve instruction throughput.

The most prominent deployment of the R4300i was in the Nintendo 64, where it operated at roughly 93.75 MHz. The CPU worked alongside the console’s Reality Coprocessor subsystem to handle graphics and audio tasks, forming the core of the system’s processing capabilities. Beyond the Nintendo 64, the R4300i appeared in various NEC-based embedded and arcade platforms during the 1990s.

Legacy and impact: The R4300i represented NEC’s continuation of the MIPS III line and contributed to the popularity of MIPS-based cores in gaming and embedded markets. It was eventually superseded by newer MIPS designs as processor technology advanced.