Pagewalk

Pagewalk is the process by which a computer's memory management unit translates a virtual address into a physical address by traversing the system’s page tables. It typically occurs when a virtual address is accessed and there is no valid translation in the translation lookaside buffer (TLB), or when the operating system needs to fault in a page.

In systems with hierarchical page tables, a page walk starts at the top-level page table and descends through intermediate tables to reach the final page table entry. Each level provides a portion of the virtual address as an index, and the corresponding page table entries (PTEs) contain the physical frame number and access flags (present, read/write, user/supervisor, etc.). The walk continues until a valid, present PTE is found, at which point the physical address can be assembled. If an intermediate PTE indicates an invalid entry or the final PTE marks a page as not present, a page fault is generated and the operating system handles bringing the page into memory or signaling an error.

Performance implications are significant: page walks are slower than a TLB hit, so modern CPUs employ mechanisms such as a page-walk cache or optimized walk hardware to reduce latency. Large pages, ASIDs (address space identifiers), and TLB hierarchies can also mitigate the cost of walking the page table.

Typical architectures that use page walks include x86-64 with a four-level paging structure (PML4, PDPT, PD, PT) and various other models that employ multi-level or inverted page tables. See also virtual memory, page table, TLB, and page fault.