Nonsynthesizeable

Nonsynthesizeable refers to a property of certain code constructs or designs in hardware description languages (HDLs) that cannot be translated into actual physical hardware. This means that while such code can be simulated and verified logically, it is not suitable for direct implementation on an FPGA or in an ASIC.

The concept of nonsynthesizeable code is crucial in hardware design. HDL compilers, also known as synthesis tools, are responsible for converting the abstract description of a digital circuit into a netlist of logic gates and flip-flops that can be fabricated. If a construct is nonsynthesizeable, the synthesis tool will either flag an error, issue a warning, or interpret it in a way that might not be intended, leading to unexpected behavior in the final hardware.

Common examples of nonsynthesizeable constructs include certain procedural blocks, delays, infinite loops, and constructs that rely on precise timing that cannot be mapped to synchronous hardware elements. For instance, the use of a non-blocking assignment (`<=`) within an `always_comb` block in Verilog or SystemVerilog is often nonsynthesizeable because it implies sequential behavior that doesn't fit the combinational logic intended. Similarly, direct instantiation of certain system tasks or models that are purely for simulation purposes are nonsynthesizeable.

Understanding and avoiding nonsynthesizeable code is essential for efficient and correct hardware design flows. Designers must distinguish between code intended for simulation and verification, and code that needs to be synthesized into hardware. This distinction ensures that designs can be reliably implemented on physical devices.