MUXes

A multiplexer, often abbreviated MUX, is a combinational circuit that selects one of several input data lines and forwards the selected input to a single output line. The selection is controlled by one or more select signals. An N-input MUX has N data inputs and uses log2(N) select lines. For example, a 4-to-1 MUX uses two select lines to choose among four inputs.

Implementation commonly uses a layer of AND gates to gate each input with a unique combination of the select signals, followed by an OR gate that combines the gated inputs. In practice, multiplexers can also be built with pass-transistor networks or transmission gates, especially in integrated circuit design. A wide data path can be implemented by using parallel copies of a smaller MUX, or by using a single wide MUX that operates on multi-bit data.

Data width is a separate consideration: a k-input, w-bit MUX selects one of k w-bit data values, effectively w parallel 1-bit MUXes. The number of select lines is log2(k). There are common variants such as 2-to-1, 4-to-1, 8-to-1, and so on, as well as MUXes with enable inputs.

Relation to demultiplexers: a demultiplexer performs the inverse operation, routing a single input to one of several outputs based on the select lines. MUXes are widely used to route data within processors, memory interfaces, I/O subsystems, and digital signal paths, enabling conditional data-path selection without storing state. They are purely combinational and introduce a propagation delay depending on size and implementation.