Loadlinked

Loadlinked (LL) is a memory-access instruction used in several RISC architectures as part of the load-linked/store-conditional (LL/SC) synchronization mechanism. An LL reads a value from a memory address and establishes a reservation on that address, intending that a subsequent store to the same address will be permitted only if the reservation remains valid.

The corresponding store-conditional (SC) attempts to write the new value to the address but will only succeed if no intervening write has occurred to that address since the LL, and if the processor's reservation is still valid. If the reservation is broken, the SC fails and no write occurs. In many implementations the SC returns an indication of success or failure, and software typically repeats the load-link and store-conditional sequence until the store succeeds.

Usage: LL/SC is used to implement atomic read-modify-write operations such as atomic increments, test-and-set, and compare-and-swap-like primitives without requiring a full memory barrier. A common pattern is: value = LL(address); new = value + 1; while (SC(address, new) == failure) { value = LL(address); new = value + 1; }.

Architecture examples: MIPS uses ll and sc; ARM uses LDREX and STREX (together forming LL/SC semantics in newer architectures); PowerPC uses lwarx and stwcx. The exact semantics and failure codes vary by ISA, but the basic idea is the same across these families.

Limitations and notes: The reservation may be cleared by any intervening write to the address, by cache-coherence actions, or by context switches; LL/SC can be sensitive to interrupts and cache-line sharing. They can be harder to reason about than compare-and-swap in some systems. Some architectures implement CAS as a preferred primitive. Proper memory ordering primitives or barriers may be required around the sequence.