cachecoherence

Cache coherence is a property of a shared-memory multiprocessor system that ensures that reads and writes to shared memory yield a consistent view across all processors. In systems with private caches, copies of the same memory location may coexist in several caches. When one processor writes, other caches may have stale copies, leading to incorrect results. Cache coherence protocols coordinate actions so that the most recent value is seen by all processors.

Two broad approaches are used: snooping and directory-based protocols. Snooping relies on a common bus or interconnect where caches listen to memory transactions and invalidate or update copies as needed. Directory-based schemes use a centralized or distributed directory that tracks which caches hold copies of each memory line and sends targeted invalidations or updates.

Common coherence protocols use a small finite state machine for each cache line. MSI (Modified, Shared, Invalid) allows a line to be Modified by one cache, Shared in several caches, or Invalid. MESI adds an Exclusive state for clean copies in only one cache, enabling silent upgrades. Other variants include MOESI and MERSI, which add states for ownership or exclusive sharing. Transactions typically include read miss, write miss, and the corresponding invalidate or update messages.

Coherence is distinct from, but related to, memory consistency models. Coherence ensures a single, coherent view of memory values, while the model defines the permitted ordering of operations. Coherence overhead can affect latency and bandwidth, and poses scalability challenges in many-core and NUMA systems. Techniques such as hierarchical caches and efficient directory structures help mitigate traffic.