CXL

Compute Express Link (CXL) is an open industry standard for high-speed interconnect between central processing units, memory devices, and accelerators. Developed by the CXL Consortium, CXL enables cache-coherent memory access and memory pooling across devices, allowing components such as GPUs, FPGAs, and smart NICs to access host memory efficiently. CXL is built on the PCI Express physical layer, using PCIe signaling, but defines its own protocol layers to support coherent memory sharing and device management.

CXL defines three sub-protocols that establish its architecture. CXL.io handles I/O management, device discovery, and protocol mapping. CXL.mem provides cache-coherent memory access between the host and memory devices, enabling direct memory expansion with coherent access. CXL.cache supports cache-to-cache coherency between devices to improve data sharing and reduce latency. Together, these layers enable memory disaggregation and pooling, where memory can be shared across multiple devices or host CPUs through a CXL fabric, which may include switches and multiple endpoints.

The ecosystem includes processors, memory expanders, accelerators, and CXL switches that form disaggregated memory fabrics. Adoption aims to reduce memory bottlenecks in data centers and improve efficiency for workloads such as AI inference and training, high-performance computing, and analytics by enabling flexible, scalable memory resources and coherent access.

History and status: the CXL Consortium, founded to standardize this interconnect, released multiple versions of the specification starting in 2019, with later updates adding memory pooling, switching, and scalable fabrics. Ongoing work continues to expand adoption, interoperability, and feature sets across platforms and vendors.