Aarch64

Aarch64 is the 64-bit execution state of the ARMv8-A architecture, commonly referred to as ARM64. It defines a 64-bit instruction set, registers, and system features designed for high performance across mobile, embedded, and server-class devices. Aarch64 coexists with the earlier 32-bit Aarch32 execution state, providing backward compatibility for older ARMv7 code.

In Aarch64, the architectural state includes 31 general-purpose registers named X0–X30, with X30 typically serving as the link register, a dedicated zero register XZR, a stack pointer SP, and a program counter. Instructions use a fixed 32-bit encoding in the A64 instruction set. The architecture supports large virtual address spaces, multi-level page tables, ASID tagging, and TLBs to enable efficient virtual memory and context switching. Endianness is configurable, with most implementations operating in little-endian mode.

Key features of Aarch64 include Advanced SIMD (NEON) for vector and floating-point processing, and optional Cryptography Extensions. Many implementations also support Scalable Vector Extension (SVE) for HPC workloads. The architecture provides hardware-assisted virtualization, delivering an EL2 hypervisor mode, as well as security features such as TrustZone for trusted execution environments.

Software compatibility and ecosystem are broad. AArch32 provides a compatibility path for 32-bit ARM code within an Aarch64 system. Toolchains and operating systems widely support Aarch64, including Linux, Android, and Windows on ARM. The ecosystem also encompasses emulation and virtualization solutions (for example, QEMU and various hypervisors) and a mature set of development tools (GCC, LLVM/Clang, binutils).

Overall, Aarch64 represents ARM’s 64-bit evolution, delivering substantial performance and efficiency improvements while maintaining backward compatibility with legacy 32-bit software.