latchup

Latchup is a short-circuit condition that can occur in integrated circuits, especially CMOS, when a parasitic thyristor network inside the device becomes forward-biased and conducts a large current from supply to ground. This parasitic network behaves like a pnpn thyristor formed by the p- and n-doped regions and their connections within the well and substrate. When triggered, a low-impedance path is created that draws substantial current, potentially causing device overheating or destruction if the current is not limited or the supply removed.

The mechanism involves a parasitic four-layer structure consisting of two bipolar transistors (a pnp and an npn) that provide positive feedback. In a CMOS process, diffusion and well arrangements around transistors can form this structure near the interface of the substrate and wells. Latchup can be triggered by transient voltages, high-energy particles, your noise spikes, voltage supplies outside specified ranges, or radiation, which inject carriers and forward-bias the transistor junctions. Once initiated, the thyristor can sustain itself even after the original trigger is removed, until the current is interrupted or the device is reset by removing power.

Prevention and mitigation rely on circuit and layout techniques. Guard rings and well ties isolate and pin the parasitic structures to known potentials, while adequate substrate and well contacts help prevent unintended forward biasing. Design practices include using epitaxial layers, opting for silicon-on-insulator or triple-well processes, and implementing proper ESD and overvoltage protection. Power-down procedures and current limiting can also help recover from latchup if it occurs. Latchup remains a key reliability consideration in CMOS and other high-density IC technologies.