TLBS

A translation lookaside buffer (TLB) is a small, fast cache used by a computer’s memory-management unit to speed the translation of virtual addresses to physical addresses. It stores recent page-table entries so that common translations can be completed without walking the full page table in memory.

A TLB entry typically contains the virtual page number as the key, the corresponding physical frame number, access permissions, a valid bit, and often an identifier for the address space or process (ASID) to distinguish translations from different processes. TLBs are usually implemented as fully associative or set-associative caches and are considerably smaller than the page table they cache.

Operation begins when the CPU references a virtual address. The MMU checks the TLB for a matching translation. If present (a TLB hit), the physical address is formed and memory access proceeds quickly. If the translation is not in the TLB (a TLB miss), the MMU performs a page-table walk in memory to obtain the translation, loads it into the TLB, and then restarts the access. A missing or invalid page-table entry can trigger a page fault or an exception, handled by the operating system.

TLBs are per-core or per-hardware context and may require invalidation or reloading during context switches. To avoid flushing all entries on every switch, many systems tag entries with ASIDs and selectively invalidate them. When page protections or mappings change, the OS may issue TLB shootdowns to other cores to maintain coherence.

In virtualization scenarios, second-level translations (such as EPT or NPT) add another level of translation, and TLB maintenance becomes more complex. Modern processors provide hardware support to tag, invalidate, and synchronize TLBs across cores and virtual machines, reducing overhead while preserving isolation and correctness.

TLBs significantly improve memory access performance by reducing the latency of address translation, especially under strong locality of reference.