Retimed

Retimed is an adjective used in digital circuit design to describe a circuit, register chain, or timing scenario in which the location of storage elements has been altered to change timing characteristics while preserving functionality. The term arises from applying the retiming technique to synchronous designs.

Retiming is an optimization technique formalized by Leiserson and Saxe in the 1980s. It moves registers across combinational logic blocks, effectively redistributing latency among pipeline stages. The goal is to reduce the required clock period or balance work between stages without changing the circuit's input-output behavior.

Practically, a circuit is modeled as a graph of registers connected by combinational paths. Legal transformations relocate a register boundary across a node if the operation preserves the node's functional equivalence and does not introduce cycles. The process iteratively applies safe moves until no further timing improvements are possible under the given constraints.

Retimed designs are common in FPGA synthesis and ASIC optimization, where deeper pipelines can improve throughput, and clock frequencies can be increased. It is used during high-level synthesis and logic optimization to meet timing budgets while controlling area and power impact.

Not all circuits benefit from retiming; some paths may become unbalanced, increasing register counts or power consumption. Retiming must account for clock skew, enable signals, and memory elements, and may interact with other optimizations such as resource sharing and retiming under latency constraints.

See also: retiming, pipelining, digital logic optimization, clock period.