RGMII

RGMII, or Reduced Gigabit Media Independent Interface, is a standard for connecting the Media Access Control (MAC) layer to the physical layer (PHY) in Ethernet devices. It was developed to reduce the pin count and routing complexity compared with GMII while still supporting gigabit Ethernet.

RGMII achieves its reduced pin count by using a 4-bit data bus in each direction (Tx and Rx) and by transferring data on both edges of a 125 MHz reference clock, which provides the necessary throughput for 1 gigabit per second. In practice, this means the interface carries a small number of data and control signals along with dedicated clock lines for transmit and receive paths. While data paths are 4 bits wide, signaling is often described as DDR (dual data rate) to emphasize the dual-edge operation.

Signals and layout considerations: RGMII typically uses TXD[3:0] and RXD[3:0] for data, along with a set of control and timing signals and separate TXC and RXC clock lines. Because timing skew between data and clock is critical at 125 MHz, PCB layout must minimize skew and maintain matched trace lengths for the differential clock paths and data lines. Power domains and voltage levels vary by device, with many parts targeting 3.3V logic, though lower-voltage options exist.

Relation to other interfaces: GMII is the original wide interface, RMII reduces pins further but operates at a lower speed, and RGMII sits between them, offering a balance of pin count and gigabit capability. RGMII is widely supported in modern MACs and PHYs for 1000BASE-T applications.