Make

Make is a build automation tool that uses instructions called Makefiles to determine which parts of a software project must be rebuilt when source files change. It abstracts the process of compiling, linking, and installing by expressing relationships between targets (such as executables or libraries), their dependencies (source or object files), and the commands needed to create or update them. Make is widely used on Unix-like systems and is available in various forms on other platforms.

The original program was developed for Unix in the late 1970s by Stuart Feldman at Bell Labs. Over time, GNU make, a reimplementation and extension, became the de facto standard in the open-source world and is distributed as part of the GNU project. Other make variants exist, such as BSD make and Microsoft NMake, each with its own features and quirks. Make has evolved to handle large projects by supporting variables, pattern rules, and include files, while remaining usable for simple tasks.

A Makefile describes targets, dependencies, and recipes. A typical rule takes the form: target: dependencies followed by one or more recipe lines, which must be indented with a tab. Variables can be defined and reused, and automatic variables such as $@ (the target), $< (the first prerequisite), and $^ (all prerequisites) simplify recipes. Pattern rules enable generic building with placeholders like %.o: %.c. Makefiles can also include other Makefiles and define phony targets, such as clean, that do not correspond to real files.

Common usage involves invoking make to build default targets, or specifying a particular target, e.g., make, make all, make clean, or make install.