Makefiles

Makefiles are text files used by the Make program to describe how to build a software project. They specify targets, dependencies, and shell commands to produce files. Originating on Unix, Makefiles support incremental builds by rebuilding only out-of-date files.

A rule consists of a target, prerequisites, and a recipe. The form is: target: prerequisites newline tab recipe. The target is the file to be built; phony targets such as clean perform actions without producing a file. Recipes run in the shell and may use variables.

Variables control configuration. They can be defined with =, :=, or ?= and referenced as $(VAR). Common choices include CC for the compiler and CFLAGS for flags. Automatic variables such as $@ and $< are available inside recipes.

Make supports pattern and implicit rules, and includes. Pattern rules use % to describe how to build several targets from related prerequisites. Includes allow splitting builds across files. Functions such as $(wildcard ...), $(shell ...), foreach, and ifeq enable dynamic behavior.

Usage practices include keeping a clean Makefile, using phony targets, and isolating configuration from rules. Enabling parallel builds with -j speeds large projects, while portability considerations suggest avoiding shell-specific features and adapting for different environments.

Makefiles are widely used across languages and toolchains. They can be extended with include files and conditional parts, and many projects combine Make with higher-level build systems.