MTRR

Memory Type Range Registers (MTRR) are a set of x86 model-specific registers that govern the caching behavior of physical memory ranges. By associating different physical address ranges with specific memory types, MTRRs help the processor apply appropriate caching rules to regular RAM, memory-mapped I/O, and device memory, balancing performance with data integrity. They work alongside the processor’s caching architecture and are complemented by mechanisms such as the Page Attribute Table (PAT).

There are two kinds of MTRRs: fixed and variable. Fixed MTRRs control a small number of predefined regions with a fixed cache type. Variable MTRRs consist of pairs of registers that define a base address and a mask, enabling multiple ranges to be assigned a particular memory type (for example uncacheable UC, write-combining WC, write-through WT, or write-back WB). A default memory type is stored in the MTRRdefType register and applies to addresses not covered by any MTRR range when MTRRs are enabled.

Setting MTRRs is typically the responsibility of the operating system or firmware. The processor enforces consistency rules to prevent conflicting types; overlapping ranges follow defined resolution rules. Misconfiguration can degrade performance or cause data integrity problems, so operating systems usually rely on PAT for finer-grained caching control and use MTRRs primarily for compatibility with legacy devices.

In modern systems, MTRRs are often supplemented or superseded by PAT and related mechanisms, and virtualization environments may impose restrictions on MTRR programming. Nevertheless, MTRRs remain a fundamental tool for controlling the caching behavior of memory ranges on many x86 processors.