Deassertion

Deassertion is the act of returning a signal or condition from an asserted (active) state to its inactive state. In digital logic, a signal is often described as asserted when it is in its designated active state, which for many designs is logic high; deassertion is the transition to the opposite state. Deassertion is a key part of control sequences, such as releasing a device from reset or disabling an enable signal.

In hardware design, deassertion can be synchronous or asynchronous. A reset deassertion releases circuitry after a clock edge; asynchronous deassertion can occur immediately. Designers must consider timing to avoid glitches or metastability when a deasserting signal is deactivated near a clock edge.

In protocols and handshaking, deassertion of request or grant signals indicates completion or cancellation of an operation; proper sequencing ensures data integrity.

In verification, assertions express expected properties; deassertion can refer to turning off an assertion, or to the negation of an asserted condition in a trace. In software, assertion mechanisms may be enabled or disabled; deactivating them prevents runtime checks.

Because polarity matters, it is important to state whether a signal is active-high or active-low; a signal that is deasserted for a low-active line may be represented as a high logic level, and vice versa.