CacheHit

CacheHit is the event in which a data request is satisfied by data already stored in a cache, avoiding access to slower storage. A cache hit indicates the data is present in the cache and can be delivered with low latency, while a cache miss occurs when the data is not present and must be fetched from a lower level of storage, such as main memory, a disk, or a remote service, after which it may be cached for future requests.

Cache systems operate in various domains, including CPU caches (L1, L2, L3), web caches (browsers, proxies, CDNs), and application or database caches (in-memory stores like Redis or Memcached). The probability of a hit, the cache hit rate, depends on cache size, data access patterns, and replacement policies such as LRU, LFU, or ARC that decide what to evict.

Performance is summarized by the cache hit rate and the associated latency reduction. A common metric is AMAT, which equals the cache access time plus the miss rate times the penalty to fetch from the next level. Higher hit rates reduce average access time and bandwidth usage, while misses incur additional latency.

In multi-core or distributed caches, coherence and consistency issues can affect hits, and cache warm-up or cold-start effects influence early performance measurements.

Examples: A processor requesting a memory block satisfied by L1 cache is a hit; otherwise the request proceeds to L2 or main memory. Understanding hit rates helps optimize memory layout, caching strategies, and system design.

Related concepts include cache miss, locality of reference, eviction policy, and cache coherence.