65C02

The 65C02 is a CMOS 8-bit microprocessor designed by Western Design Center (WDC) as an enhanced, backward-compatible successor to the 6502. Introduced in the early 1980s, it aimed to combine the familiarity of the 6502 with improved reliability, lower power consumption, and practical enhancements for embedded applications.

The 65C02 preserves the core architecture of the 6502, including its A, X, and Y registers, the 8-bit processor status register, and a 16-bit address space. Software written for the 6502 generally runs on the 65C02 with little or no modification, making it attractive for existing systems seeking CMOS benefits and modest performance gains. The CMOS design reduces dynamic power usage and can operate at higher clock rates in some implementations, compared with the original NMOS 6502.

Enhancements and new features include the introduction of additional instructions and capabilities. Notably, the 65C02 adds STZ, a Store Zero instruction that clears a memory location by writing zero, and new options for handling the index registers with PHX and PHY (push X and push Y) and PLX and PLY (pull X and pull Y) to and from the stack. In addition to these, the 65C02 includes fixes to known design bugs in the original 6502 and excludes some unreliable undocumented opcodes, improving overall reliability.

Applications and legacy: The 65C02 found use in a variety of embedded systems and consumer electronics during the 1980s and beyond, providing a CMOS alternative to the 6502 where lower power and higher reliability were desirable. It also influenced later CMOS versions and derivatives in the 65xx family, including subsequent enhancements by WDC.