tRCD

tRCD stands for Row Address to Column Address Delawn, and it is a DRAM timing parameter that specifies the minimum number of memory clock cycles between activating a row (RAS) and issuing a read or write command to a column within that row. In practice, tRCD represents the delay required to prepare the data path after a row has been opened so that a column access can occur reliably. It is typically expressed in memory clock cycles, and the corresponding time in nanoseconds depends on the memory’s operating frequency.

In the context of DDR SDRAM, tRCD is part of a set of core timings that also include tRAS (row active time) and tRP (row precharge). The three timings together influence the latency of accessing data from DRAM. A smaller tRCD reduces the latency for an initial access after a row open, while a larger tRCD can be necessary for stability at higher frequencies or with certain memory modules.

Manufacturers publish tRCD values in module specifications, and many systems expose this setting in BIOS/UEFI as part of manual or XMP-enabled memory timing profiles. Real-world effects of changing tRCD include changes to random-access latency and, to a broader extent, overall memory performance. When tuning, users balance tRCD with other timings and system stability, as aggressive tuning can lead to errors if the memory or controller cannot reliably operate at the selected values.