sixtransistor

Six-transistor (6T) SRAM is a standard static random-access memory cell design used for storing a single binary bit. The cell uses six transistors in total: two cross-coupled inverters that form a bistable latch, and two NMOS access transistors that connect the storage nodes to the bit lines when a word line is activated. The storage nodes are usually labeled Q and Q̄, and the bit lines are BL and BL̄.

The two cross-coupled inverters provide the memory function, holding either a high or a low state as long as power is supplied. The two access transistors serve as gate-controlled passes that allow writing to or reading from the cell. When a word line is asserted, the bit lines drive the storage nodes to the desired state during a write operation. For reading, a sense amplifier detects the relative voltage on the bit lines after the word line is activated, while the cross-coupled latches help maintain stability during the read.

Compared with some alternative SRAM configurations, the 6T cell offers good density because it uses a compact six-transistor arrangement. However, it is sensitive to read disturbances, since a read operation briefly connects the storage nodes to the bit lines. This requires careful circuit design, transistor sizing, and sense-amplifier timing to ensure reliable operation across process, voltage, and temperature variations. Variants such as 8T and higher-transistor SRAM cells separate read and write paths to improve reliability, at the cost of larger cell area.

Six-transistor SRAM remains a fundamental building block in on-chip caches and memory arrays, balancing density and performance in many integrated circuits.