pipelineADCs

Pipeline analog-to-digital converters (pipeline ADCs) are high-speed ADC architectures that divide the conversion into a sequence of stages. Each stage performs a coarse conversion on its portion of the digital word, generates a residual analog signal that represents the remaining information, and forwards the residual to the next stage through a register. The result is a high-throughput converter produced by overlapping conversions across stages, enabling high sample rates at moderate power.

Most pipeline stages resolve about 1.5 or 2 bits per stage. In a typical 1.5-bit stage, a small sub-ADC determines the sign and a coarse magnitude, a sub-DAC reconstructs the input and produces a residue, which is amplified and sent to the next stage. Between stages are latches to hold intermediate code, preserving synchronization. The final stage provides the remaining bits, and a digital correction network combines stage outputs to form the final N-bit word. Capacitive DACs are commonly used in the stages, along with precision comparators and residue amplifiers.

Throughput in pipeline ADCs is high because stages operate in parallel on successive samples; overall latency equals the number of stages times the clock period, whereas the throughput can approach the clock rate. Key performance metrics include resolution (bits), SNDR/ENOB, SFDR, sampling rate, and power. Design challenges include matching errors and capacitor mismatches, which are mitigated by calibration and redundancy.

Applications include high-speed communications, RF receivers, radar, and instrumentation where fast, moderate-to-high resolution conversion is required. Pipeline ADCs are often contrasted with flash and SAR ADCs, offering favorable speed-power-area trade-offs for many systems.