interruptlatency

Interrupt latency is the time between the moment an interrupt request is generated by hardware and the moment the processor begins executing the corresponding interrupt service routine (ISR). It is a measure of how quickly a system can respond to an external or internal event that requires attention.

The latency typically includes several stages: the interrupt request being asserted, the interrupt controller acknowledging the interrupt, the processor recognizing and prioritizing the interrupt, and the dispatch of the appropriate ISR, including any necessary context switching. In many architectures, the ISR may not start immediately if interrupts are masked or if higher-priority interrupts are being serviced. The total latency is influenced by both hardware (interrupt controller design, bus architecture, and signaling) and software (priority schemes, interrupt masking, and the cost of context switching).

Common factors affecting interrupt latency include the type of interrupt controller (for example, legacy PICs, advanced programmable interrupt controllers, or I/O APICs), the use of message-signaled interrupts, interrupt nesting and preemption rules, CPU clock frequency, caching and memory access latencies, and the length and complexity of the ISR. In multi-core and multi-processor systems, latency can also depend on which core handles the interrupt and how the system binds interrupts to cores.

In real-time and safety-critical contexts, latency is often bounded and measured as worst-case or maximum latency, distinct from the overall time to complete an interrupt service. Techniques to reduce latency include using dedicated interrupt lines, high-priority interrupts, minimal and fast-path ISRs, and hardware features that support deterministic interrupt handling.