boundaryscan

Boundary scan is a method for testing interconnections on printed circuit boards and for in-system programming of devices by using the JTAG boundary-scan architecture defined in IEEE 1149.1. It embeds boundary scan cells at the I/O boundary of an integrated circuit so that the states of pins and nets connected to those pins can be observed and controlled through a serial data path known as the boundary scan chain. By daisy-chaining the boundary scan access ports of multiple devices on a board, test data can be shifted in and out without physical probes, enabling fault isolation and functional testing.

The standard interface, commonly referred to as JTAG, provides a Test Access Port (TAP) with signals such as TCK (clock), TMS (mode select), TDI (data in), TDO (data out), and an optional TRST (reset). Each device contains a boundary scan register alongside optional registers (bypass, device ID, etc.). During testing, a test logic state machine controls operations such as Capture, Shift, Update, and Run-Test/Idle. In Capture mode, boundary scan cells capture system state; in Shift mode, data is shifted through the chain; in Update mode, cells update the system I/O based on the shifted data.

History and scope: boundary scan was developed by the Joint Test Action Group in the 1980s and standardized as IEEE 1149.1 in 1990, which popularized the term JTAG. The technique remains widely used for manufacturing tests, board-level fault isolation, in-system programming, firmware updates, and diagnostics on complex electronic assemblies.

Limitations and considerations: effective boundary-scan testing requires boundary-scan-enabled devices and appropriate test access, and coverage may be incomplete for non-I/O circuits or highly analog components. Complex boards may require segmentation of test access and external tooling.