SRST

SRST stands for System Reset. In electronics and testing contexts, SRST refers to a dedicated reset input used to bring the target device's system logic into a known default state during boundary-scan or in-system testing. The signal is distinct from TRST, the Test Reset used to initialize the JTAG TAP controller; SRST is typically used to reset the device’s core logic or system peripherals, so that subsequent JTAG operations occur from a defined state. The SRST line may be active-high or active-low, and its electrical characteristics (level vs edge, asynchronous vs synchronous assertion) are device-specific.

In practice, SRST is commonly exposed on device packages that support boundary-scan, including many FPGAs and microcontrollers with in-system programming features. An external supervisor can assert SRST during test or programming to ensure a clean start; releasing SRST allows the device to resume normal operation after the test sequence. Because SRST is not required by IEEE 1149.1 and its behavior varies by vendor, designers must consult the device datasheet for the exact behavior, timing, and pin configuration.

SRST is used in conjunction with boundary scan to improve test robustness, enabling system resets without cycling power if supported. It is part of the broader JTAG boundary-scan ecosystem, which also includes TRST, TCK, TMS, and the data and instruction registers. See also JTAG, boundary scan, IEEE 1149.1.