SPI

Serial Peripheral Interface (SPI) is a synchronous serial communication protocol used for short-distance communication, primarily in embedded systems. It uses a master/slave architecture, typically with a single master and one or more peripheral slaves. A standard SPI bus employs four wires: SCK (serial clock from the master), MOSI (master out, slave in), MISO (slave out, master in), and SS (slave select or chip select). Some implementations include 3-wire variants where data lines are bidirectional or shared.

Communication on SPI is full duplex and driven by the master clock. Data is shifted out on MOSI and sampled on MISO on edges defined by CPOL and CPHA, referred to as SPI modes 0 through 3. CPOL determines the idle clock level, while CPHA determines which edge captures data. Each slave selects via its SS line; only the active slave responds, and others remain tri-stated.

SPI is not a formal standard and has many variants, but it is typically faster and has lower protocol overhead than I2C, at the cost of requiring more wiring and device-specific timing. It is widely used for memory devices (such as flash), sensors, display controllers, ADCs and DACs, and other peripherals.

Higher-throughput variants exist, such as Quad SPI (QSPI) and Dual SPI, which use multiple data lines to increase bandwidth. Common considerations include ensuring compatible voltage levels when devices operate at different supplies, keeping MISO tri-stated when no device is selected, and correctly aligning clock polarity and phase across devices.