SARADC

SARADC stands for successive-approximation-register analog-to-digital converter. It is a type of ADC that converts an analog input to a digital code by performing a binary search using a DAC and a comparator, controlled by a successive-approximation register.

Most SAR ADCs employ a capacitor-based DAC, typically a binary-weighted capacitor array whose bottom plate is driven by the SAR logic. During the sampling phase, the input is sampled onto the capacitor array. In the conversion phase, the bottom plates are reconnected to reference voltages (Vref and ground) to generate DAC outputs. The comparator compares the DAC output with the input, and the SAR bit decisions are set MSB first; each cycle fixes one bit, halving the remaining uncertainty until the final code is produced.

Performance and design considerations: resolution commonly 8 to 18 bits; sample rates range from a few kS/s to several hundred MS/s in modern devices; power efficiency is a key advantage. Design challenges include capacitor mismatches, comparator offset and noise, and kickback from the DAC into the input. Layout techniques, calibration, and sometimes dynamic element matching are used to improve linearity (INL/DNL) and monotonicity.

Variants and applications: SAR ADCs are widely used in microcontrollers, data acquisition systems, and instrumentation where moderate speed and high resolution with low power are required. They may be implemented as asynchronous or synchronous devices, and combined with time-interleaving or pipeline stages for higher throughput. Their simplicity and predictable performance make them a standard choice in many embedded and low-power applications.