PowerGating

Power gating is a circuit technique used to reduce power consumption by selectively disconnecting the power supply or ground from idle parts of an integrated circuit. It is commonly employed in modern microprocessors, system-on-chips, and other digital ICs to reduce leakage current in standby or low-activity modes. Power gating complements clock gating by reducing power draw from idle blocks even when clocks may be running.

Implementation typically uses a sleep transistor, a high-threshold device placed between the block and the supply rail (or ground). When the block is active, the sleep transistor is turned on, supplying full voltage. When the block is idle, the sleep transistor is turned off, isolating the block and greatly reducing leakage current. To prevent unwanted leakage through IOs, isolation cells and sometimes level shifters are used. Some designs retain the block's state by using retention flip-flops or small capacitors to hold critical data.

Wake-up from a gated state introduces latency, due to turning on the sleep transistor and reestablishing the block’s supply and IO levels. This latency, along with area and design complexity, is a key design trade-off. Power gating is typically organized into power islands or domains, allowing selective gating of whole regions while keeping others active.

Applications include mobile CPU cores, GPUs, and SoCs, where long idle periods benefit from reduced leakage. The approach demands careful design for testability, isolation during off-states, and safe state retention. Trade-offs involve area, fabrication complexities, and wake-up performance, but power gating remains a central technique for reducing standby power in modern deep-submicron and finFET processes.